september 2005 ? 2005 fairchild semiconductor corporation FDD6635 rev. c(w) www.fairchildsemi.com FDD6635 35v n-channel powertrench ? mosfet general description this n-channel mosfet has been produced using fairchild semiconductor?s proprietary powertrench technology to deliver low rdson and optimized bvdss capability to offer superior performance benefit in the applications. applications ? inverter ? power supplies features ? 59 a, 35 v r ds(on) = 10 m @ v gs = 10 v r ds(on) = 13 m @ v gs = 4.5 v ? fast switching ? rohs compliant g s d to-252 d-pak (to-252) s g d absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain-source voltage 35 v v ds(avalanche) drain-source avalanche voltage (maximum) (note 4) 40 v v gss gate-source voltage 20 v i d continuous drain current @t c =25c (note 3) 59 a @t a =25c (note 1a) 15 pulsed (note 1a) 100 power dissipation @t c =25c (note 3) 55 @t a =25c (note 1a) 3.8 p d @t a =25c (note 1b) 1.6 w t j , t stg operating and storage junction temperature range ?55 to +150 c thermal characteristics r jc thermal resistance, junction-to-case (note 1) 2.7 c/w r ja thermal resistance, junction-to-ambient (note 1a) 40 c/w r ja thermal resistance, junction-to-ambient (note 1b) 96 c/w package marking and ordering information device marking device package reel size tape width quantity FDD6635 FDD6635 d-pak (to-252) 13?? 12mm 2500 units FDD6635 35v n-channel powertrench ? mosfet
FDD6635 rev. c(w) www.fairchildsemi.com electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units drain-source avalanche ratings e as drain-source avalanche energy (single pulse) v dd = 35 v, i d = 15 a, l=1mh 113 mj i as drain-source avalanche current 15 a off characteristics (note 2) bv dss drain?source breakdown voltage v gs = 0 v, i d = 250 a 35 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 32 mv/ c i dss zero gate voltage drain current v ds = 28 v, v gs = 0 v 1 a i gss gate?body leakage v gs = 20 v, v ds = 0 v 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 1 1.9 3 v v gs(th) t j gate threshold voltage temperature coefficient i d = 250 a, referenced to 25 c ?5 mv/ c r ds(on) static drain?source on?resistance v gs = 10 v, i d = 15 a v gs = 4.5 v, i d = 13 a v gs = 10 v, i d = 15 a, t j =125 c 8.2 10.2 12.4 10 13 16 m g fs forward transconductance v ds = 5 v, i d = 15 a 53 s dynamic characteristics c iss input capacitance 1400 pf c oss output capacitance 317 pf c rss reverse transfer capacitance v ds = 20 v, v gs = 0 v, f = 1.0 mhz 137 pf r g gate resistance v gs = 15 mv, f = 1.0 mhz 1.4 switching characteristics (note 2) t d(on) turn?on delay time 11 20 ns t r turn?on rise time 6 12 ns t d(off) turn?off delay time 28 45 ns t f turn?off fall time v dd = 20 v, i d = 1 a, v gs = 10 v, r gen = 6 14 25 ns q g (tot) total gate charge, v gs = 10v 26 36 nc q g total gate charge, v gs = 5v 13 18 nc q gs gate?source charge 3.9 nc q gd gate?drain charge v ds = 20 v, i d = 15 a 5.3 nc FDD6635 35v n-channel powertrench ? mosfet
FDD6635 rev. c(w) www.fairchildsemi.com d r p ds(on) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units drain?source diode characteristics v sd drain?source diode forward voltage v gs = 0 v, i s = 15 a (note 2) 0.8 1.2 v trr diode reverse recovery time 26 ns qrr diode reverse recovery charge if = 15 a, dif/dt = 100 a/s 16 nc notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. a) r ja = 40c/w when mounted on a 1in 2 pad of 2 oz copper b) r ja = 96c/w when mounted on a minimum pad. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0% 3. maximum current is calculated as: where p d is maximum power dissipation at t c = 25c and r ds(on) is at t j(max) and v gs = 10v. package current limitation is 21a 4. bv(avalanche) rating is guaranteed if device is operated within the uis soa boundary of the device. FDD6635 35v n-channel powertrench ? mosfet
FDD6635 rev. c(w) www.fairchildsemi.com typical characteristics 0 10 20 30 40 50 60 70 80 00.511.522.53 v ds , drain-source voltage (v) i d , drain current (a) 3.5v v gs =10v 4.0v 3.0v 4.5v 6.0v 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 0 1020304050607080 i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = 3.5v 4.0v 6.0v 4.5v 5.0v 10v figure 1. on-region characteristics fi gure 2. on-resistance variation with drain current and gate voltage 0.6 0.8 1 1.2 1.4 1.6 1.8 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistance i d = 15a v gs = 10v 0.005 0.009 0.013 0.017 0.021 0.025 0.029 246810 v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = 7.5a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature figure 4. on-resistance variation with gate-to-source voltage 0 10 20 30 40 50 60 70 80 1.522.533.544.5 v gs , gate to source voltage (v) i d , drain current (a) t a =-55 o c 25 o c v ds = 5v 125 o c 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 v sd , body diode forward voltage (v) i s , reverse drain current (a) t a = 125 o c 25 o c -55 o c v gs = 0v figure 5. transfer characteristics figure 6. body diode forward voltage variation with source current and temperature fdd 6635 35 v n- c h a nn e l p o w e rtr e n c h ? m os fet
FDD6635 rev. c(w) www.fairchildsemi.com typical characteristics 0 2 4 6 8 10 0 5 10 15 20 25 30 q g , gate charge (nc) v gs , gate-source voltage (v) i d = 15a v ds = 10v 15v 20v 0 400 800 1200 1600 2000 0 5 10 15 20 25 30 v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 7. gate charge characteristics figure 8. capacitance characteristics 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 v ds , drain-source voltage (v) i d , drain current (a) dc 1s 100ms r ds(on) limit v gs = 10v single pulse r ja = 96 o c/w t a = 25 o c 10ms 1ms 100s 10s 0 20 40 60 80 100 0.01 0.1 1 10 100 1000 t 1 , time (sec) p(pk), peak transient power (w) single pulse r ja = 96c/w t a = 25c figure 9. maximum safe operating ar ea figure 10. single pulse maximum power dissipation 0 20 40 60 80 100 0.1 1 10 100 1000 t 1 , time (sec) i(pk), peak transient current (a) single pulse r ja = 96c/w t a = 25c 1 10 100 1000 1 10 100 1000 10000 t av , time in avanche(ms) i (as) , avalanche current t j = 25 o c figure 11. single pulse maximum peak current figure 12. unclamped inductive switching capability fdd 6635 35 v n- c h a nn e l p o w e rtr e n c h ? m os fet
FDD6635 rev. c(w) www.fairchildsemi.com typical characteristics 0.001 0.01 0.1 1 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r(t), normalized effective transien t thermal resistance r ja (t) = r(t) * r ja r ja = 96 c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 single pulse 0.0 0.02 0.05 0.1 0.2 d = 0.5 figure 13. transient thermal response curve thermal characterization performed using the conditions described in note 1b. transient thermal response will change depending on the circuit board design. fdd 6635 35 v n- c h a nn e l p o w e rtr e n c h ? m os fet
FDD6635 rev. c(w) www.fairchildsemi.com test circuits and waveforms v ds l r gen dut v gs i as 0.01 v dd + - tp 0v vary t p to obtain required peak i as v gs v ds l r gen dut v gs i as 0.01 v dd + - tp 0v vary t p to obtain required peak i as v gs t av t p i as v ds v dd bv dss t av t p i as v ds v dd bv dss figure 14. unclamped inductive load test circuit figure 15. unclamped inductive waveforms dut v dd v gs i g(ref) + - + - same type as dut drain current regulator 1 f 10 f 10v 50k dut v dd v gs i g(ref) + - + - same type as dut drain current regulator 1 f 10 f 10v 50k v gs q gs q gd q g 10v charge, (nc) v gs q gs q gd q g 10v charge, (nc) figure 16. gate charge test circuit figure 17. gate charge waveform v ds r l r gen dut v dd v gs pulse width 1 s duty cycle 0.1 % v gs + - v ds r l r gen dut v dd v gs pulse width 1 s duty cycle 0.1 % v gs + - t r t f t d(on) t d(off) t on t off pulse width 10% 10% 90% 10% 90% 50% 90% 50% 0v 0v v gs v ds t r t f t d(on) t d(off) t on t off pulse width 10% 10% 90% 10% 90% 50% 90% 50% 0v 0v v gs v ds figure 18. switching time test circuit figure 19. switching time waveforms fdd 6635 35 v n- c h a nn e l p o w e rtr e n c h ? m os fet
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